|
QSpace at Queen's University >
Theses, Dissertations & Graduate Projects >
Queen's Theses & Dissertations >
Please use this identifier to cite or link to this item:
http://hdl.handle.net/1974/1979
|
| Title: | System-Level Power, Thermal and Reliability Optimization |
| Authors: | Zhu, CHANGYUN |
|
|
| Keywords: | Power
Thermal
Reliability |
| Issue Date: | 2009 |
| Series/Report no.: | Canadian theses |
| Abstract: | An integrated circuit can now contain more than one billion transistors. With
increasing system integration and technology scaling, power and power-related issues
have become the primary challenges of integrated circuit design. In this dissertation,
techniques and algorithms, from system-level synthesis to emerging integration
and device technologies, are proposed to address the power and power-induced thermal
and reliability challenges of modern billion-transistor integrated circuit design.
In Chapter 1, the challenges of semiconductor technology scaling are introduced.
Chapter 2 reviews the related works. Chapter 3 focuses on the reliability optimization
issue during system-level design. A reliable application-specic multiprocessor
system-on-chip synthesis system is proposed, called TASR, which exploits redundancy
and thermal-aware design planning to produce reliable and compact circuit designs.
Chapter 4 introduces three-dimensional (3D) integration, a new integrated circuit
fabrication and integration technology. Thermal issue is a primary concern of 3D integration.
A 3D integrated circuit heat flow analytical framework is proposed in this
chapter. Proactive, continuously-engaged hardware and operating system thermal
management techniques are presented and evaluated which optimize system performance
than state-of-the-art techniques while honoring the same temperature bound.
Chapter 5 presents reconfigurable architecture design using single-electron tunneling
transistor, an ultra-low-power nanometer-scale device. The proposed design has the
potential to overcome the power and energy barriers for both high-performance computing
and ultra-low-power embedded systems. Conclusions are drawn in Chapter 6. |
| Description: | Thesis (Ph.D, Electrical & Computer Engineering) -- Queen's University, 2009-07-02 19:24:18.632 |
| URI: | http://hdl.handle.net/1974/1979 |
| Appears in Collections: | Queen's Theses & Dissertations
Electrical and Computer Engineering Graduate Theses
|
Items in QSpace are protected by copyright, with all rights reserved, unless otherwise indicated.
|
