QSpace at Queen's University >
Graduate Theses, Dissertations and Projects >
Queen's Graduate Theses and Dissertations >
Please use this identifier to cite or link to this item:
|Title: ||Radio frequency direct-digital QPSK modulators in CMOS technology|
|Authors: ||El-Gabaly, Ahmed M.|
|Keywords: ||Integrated circuits|
|Issue Date: ||2007|
|Series/Report no.: ||Canadian theses|
|Abstract: ||In this thesis, novel direct-digital Quadrature Phase Shift Keying (QPSK) modulators are proposed in low-cost Complimentary Metal Oxide Semiconductor (CMOS) technology for radio frequency (RF) wireless applications. Direct-digital architectures have attracted much attention recently as they potentially offer significant cost savings and performance benefits. A new direct-digital QPSK modulator concept is introduced where the carrier is modulated directly by digital data using Pass-Transistor Logic (PTL) circuits for a small size and low power consumption. The concept is demonstrated through the design of an L-band modulator followed by an enhanced tunable S-band version.
The proposed L-band modulator first generates all four quadrature phases of the carrier by using a 90° resistor-capacitor, capacitor-resistor (RC-CR) phase shifter followed by two 180° active baluns. One signal from the in-phase components and another from the quadrature-phase components are later selected by two PTL circuits according to the in-phase (I) and quadrature-phase (Q) digital data respectively. Finally the chosen signals are subtracted by a differential amplifier. The circuit has been experimentally demonstrated in a standard 0.18μm CMOS process, showing good performance at 1.7GHz with the data transmission rate and carrier rejection exceeding 20Mbps and 40dB respectively. The integrated circuit (IC) measures only 425μm by 850μm and consumes less than 43mW of power.
A new S-band direct-digital QPSK modulator is introduced that offers even better performance and requires fewer components. An active balun first splits the carrier into a pair of balanced signals, which are then fed to a 90° RC polyphase network generating all four differential quadrature signals. Voltage-controlled NMOS resistors are used in the RC polyphase network to fine-tune it after fabrication for the lowest possible phase error. Finally, only one of the four differential quadrature signals is selected by a PTL circuit consisting of six NMOS switches, according to both I and Q digital data values. The circuit has been experimentally demonstrated in a standard 0.18μm CMOS process showing very good performance at 2.4GHz, with the data transmission rate exceeding 56Mbps. The IC measures 720μm by 888μm with an active area of only 505μm by 610μm, and consumes less than 33mW of power.|
|Description: ||Thesis (Master, Electrical & Computer Engineering) -- Queen's University, 2007-09-26 15:42:15.243|
|Appears in Collections:||Queen's Graduate Theses and Dissertations|
Department of Electrical and Computer Engineering Graduate Theses
Items in QSpace are protected by copyright, with all rights reserved, unless otherwise indicated.