A SERIES-PARALLEL RESONANT TOPOLOGY AND NEW GATE DRIVE CIRCUITS FOR LOW VOLTAGE DC TO DC CONVERTER

Abstract

With rapid progress in microelectronics technology, high-performance Integrated Circuits (ICs) bring huge challenge to design the power supplies. Fast loop response is required to handle the high transient current of devices. Power solution size is demanded to reduce due to the size reduction of integrated circuits. The best way to meet these harsh requirements is to increase switching frequency of power supplies. Along with the benefits of increasing switching frequency, the power supplies will suffer from high switching loss and high gate charge loss as these losses are frequency dependant losses.

This thesis investigates the best topology to minimize the switching loss. The Series-Parallel Resonant Converter (SPRC) with current-doubler is mainly analyzed for high frequency low voltage high current application. The advantages and disadvantages of SPRC with current-doubler are presented. A new adaptive synchronous rectifiers timing control scheme is also proposed. The proposed timing control scheme demonstrates it can minimize body diode conduction loss of synchronous rectifiers and therefore improve the efficiency of the converter.

This thesis also proposes two families of new resonant gate drive circuits. The circuits recover a portion of gate drive energy that is total lost in conventional gate drive circuit. In addition to reducing gate charge loss, it also reduces the switching losses of the power switches. Detail operation principle, loss analysis and design guideline of the proposed drive circuits are provided. Simulation and experimental results are also presented.