A 26 GHz Phase-Locked Loop Frequency Multiplier in 0.18-um CMOS
Abstract
This thesis presents the analysis, design and characterization of an integrated
high-frequency
phase-locked loop (PLL) frequency multiplier. The frequency multiplier is novel
in its use of a low multiplication factor of 4 and a fully differential topology
for rejection of common mode interference signals.
The PLL is composed of a voltage controlled oscillator (VCO), injection-locked
frequency divider (ILFD) for the first divide-by-two stage, a static
master-slave flip-flop (MSFF) divider for the second divide-by-two stage and
a Gilbert cell mixer phase detector (PD).
The circuit has been fabricated
using a standard CMOS 0.18-um process based on its relatively low cost and ready
availability. The PLL frequency multiplier
generates an output signal at 26 GHz and is the highest operational frequency PLL
in the technology node reported to date.
Time domain phase plane analysis
is used for prediction of PLL locking range based on initial conditions of
phase and frequency offsets.
Tracking range of the PLL is limited by the inherent narrow locking range of the ILFD,
and is confirmed via experimental results.
The performance benefits of the fully differential PLL are experimentally
confirmed by the injection of
differential- and common-mode interfering signals at the
VCO control lines. A comparison of the
common- and differential-mode modulation
indices reveals that a common mode rejection ratio (CMRR) of greater than 20 dB is
possible for carrier offset frequencies of less than 1 MHz.
Closed-loop frequency domain transfer functions are used for prediction of the PLL
phase noise response, with the PLL being dominated by the reference and
VCO phase noise contributions. Regions of dominant phase noise contributions
are presented and correlated to the overall PLL phase noise performance.
Experimental verifications display good agreement and confirm the usefulness of the
techniques for PLL performance prediction.
The PLL clock multiplier has an operational output frequency of 26.204 to 26.796 GHz
and a maximum
output frequency step of 16 MHz. Measured phase noise at 1 MHz offset from the
carrier is -103.9 dBc/Hz. The PLL clock multiplier core circuit
(VCO/ILFD/MSFF Divider/PD) consumes
186 mW of combined power from 2.8 and 4.3 V DC rails.