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dc.contributor.authorBespalko, Ryan Douglas
dc.contributor.otherQueen's University (Kingston, Ont.). Theses (Queen's University (Kingston, Ont.))en
dc.date2007-07-16 13:34:41.46en
dc.date.accessioned2007-07-19T14:21:22Z
dc.date.available2007-07-19T14:21:22Z
dc.date.issued2007-07-19T14:21:22Z
dc.identifier.urihttp://hdl.handle.net/1974/452
dc.descriptionThesis (Master, Electrical & Computer Engineering) -- Queen's University, 2007-07-16 13:34:41.46en
dc.description.abstractThis thesis examines the design of high speed transimpedance amplifiers (TIAs) in low cost complimentary metal oxide semiconductor (CMOS) technology. Due to aggressive scaling, CMOS has become an attractive technology for high speed analog circuits. Besides the cost advantage, CMOS offers the potential for higher levels of integration since the analog circuits can be integrated with digital electronics on the same substrate. A 2.5 Gbps transimpedance amplifier fabricated using 0.18 um CMOS technology is presented. The TIA uses a shunt-shunt feedback topology with a cascode gain stage. Measurements of the transimpedance gain, group delay, and common mode rejection ratio are presented for the TIA and show a good match to simulated results. The noise of the TIA was characterized by measuring the noise parameters of the TIA. The noise parameters are then used to determine the input referred noise current spectral density. A 10 Gbps transimpedance amplifier fabricated using 0.18 um CMOS technology is also presented. This TIA uses a shunt-shunt feedback topology with a common source gain stage. In order to achieve the required bandwidth, the TIA uses a bandwidth extension technique called shunt-series inductive peaking. A discussion of the different methods of bandwidth extension using inductive peaking is included, and the optimal configurations for maximally flat responses are shown for shunt inductive peaking,series inductive peaking, and shunt-series inductive peaking. The TIA circuit topology is optimized using a novel noise analysis that uses a high frequency noise model for the transistor. The optimum transistor size and bias current are determined to minimize the amplifier noise. Unfortunately differential measured results are not available due to a stability problem in the amplifier. The cause of this instability is further explored and modifications to solve the problem are discussed. Single-ended results are presented and show reasonable agreement with simulated results. Differences in the results are attributed to poor modelling of the on-chip spiral inductors.en
dc.format.extent5418117 bytes
dc.format.mimetypeapplication/pdf
dc.languageenen
dc.language.isoenen
dc.relation.ispartofseriesCanadian thesesen
dc.rightsThis publication is made available by the authority of the copyright owner solely for the purpose of private study and research and may not be copied or reproduced except as permitted by the copyright laws without written authority from the copyright owner.en
dc.subjectTransimpedance amplifieren
dc.subjectCMOS technologyen
dc.subjectOptical receiveren
dc.subjectFiber to the homeen
dc.subjectIntegrated circuiten
dc.titleTransimpedance amplifier design using 0.18 um CMOS technologyen
dc.typeThesisen
dc.description.degreeMasteren
dc.contributor.supervisorFrank, Brian M.en
dc.contributor.supervisorCartledge, John C.en
dc.contributor.departmentElectrical and Computer Engineeringen


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