• Login
    View Item 
    •   Home
    • Graduate Theses, Dissertations and Projects
    • Queen's Graduate Theses and Dissertations
    • View Item
    •   Home
    • Graduate Theses, Dissertations and Projects
    • Queen's Graduate Theses and Dissertations
    • View Item
    JavaScript is disabled for your browser. Some features of this site may not work without it.

    Reliability- and Variation-Aware Placement for Field-Programmable Gate Arrays

    Thumbnail
    View/Open
    Bsoul_Assem_AM_200909_MSc.pdf (1.428Mb)
    Date
    2009-09-26
    Author
    Bsoul, Assem
    Metadata
    Show full item record
    Abstract
    Field-programmable gate arrays (FPGAs) have the potential to address scaling challenges in CMOS technology because of their regular structures and the flexibility they possess by being re-configurable after fabrication. One of the potential approaches in attacking scaling challenges, such as negative-bias temperature instability (NBTI) and process variation (PV), is by using placement techniques that are aware of these problems. Such techniques aim at placing a circuit in an FPGA such that the critical path delay is

    improved compared to the expected worst case. This can be achieved by placing NBTI-critical blocks of a circuit in areas with fast transistors in an FPGA chip.

    In this thesis, we present a detailed research effort that addresses the joint effect of NBTI and PV in FPGAs. We follow an experimental methodology in that we use actual PV data that we measure from 15 FPGA chips. The measured data is used to study the joint effect of NBTI and PV on the timing performance of circuits that are placed and routed in FPGAs. Enhancements are made to a well-known FPGA placement algorithm, T-VPlace, in order to make the placement process aware of the joint effect of NBTI and PV. Results are given for the placement and routing of Microelectronics Center of North Carolina (MCNC) benchmark circuits to show the effectiveness of the proposed techniques in addressing scaling challenges in FPGAs.
    URI for this record
    http://hdl.handle.net/1974/5217
    Collections
    • Queen's Graduate Theses and Dissertations
    • Department of Electrical and Computer Engineering Graduate Theses
    Request an alternative format
    If you require this document in an alternate, accessible format, please contact the Queen's Adaptive Technology Centre

    DSpace software copyright © 2002-2015  DuraSpace
    Contact Us
    Theme by 
    Atmire NV
     

     

    Browse

    All of QSpaceCommunities & CollectionsPublished DatesAuthorsTitlesSubjectsTypesThis CollectionPublished DatesAuthorsTitlesSubjectsTypes

    My Account

    LoginRegister

    Statistics

    View Usage StatisticsView Google Analytics Statistics

    DSpace software copyright © 2002-2015  DuraSpace
    Contact Us
    Theme by 
    Atmire NV