Topologies and Modelings of Novel Bipolar Gate Driver Techniques for Next-Generation High Frequency Voltage Regulators
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As is predicted by Moore’s law, the transistors in microprocessors increase dramatically. In order to increase the power density of the microprocessors, the switching frequency of the Voltage Regulator (VR) is expected to increase to MHz level. However, the frequency dependent loss will increase proportionally. In order to meet requirements of the next-generation microprocessors, three new ideas are proposed in this thesis. The first contribution is a new bipolar Current Source Driver (CSD) for high frequency power MOSFET. The proposed CSD alleviates the gate current diversion problem of the existing CSDs by clamping the gate voltage to a flexible negative value during turn off transition. Therefore, the proposed driver turns off the MOSFET much faster. For buck converters with 12 V input at 1MHz switching frequency, the proposed driver improves the efficiency from 80.5% using the existing CSD to 82.5% at 1.2V/30A, and at 1.3V/30A output, from 82.5% to 83.9%. The second contribution is an accurate analytical loss model of a power MOSFET with a CSD. The current diversion problem that commonly exists in CSDs is investigated mathematically. The inductor value of the CSD is optimized to achieve minimum loss for the synchronous buck converter. The experimentally measured loss matches the calculated loss very well. The efficiency with the optimal CSD inductor is improved from 86.1% to 87.6% at 12V input, 1.3V/20A output in 1MHz switching frequency and from 82.4% to 84.0% at 1.3V/30A output. The third contribution is a new inductorless bipolar gate driver for control FET of buck converters. The most important advantage of the driver presented in this thesis is that it can turn off the power MOSFETs with a negative voltage, which will significantly reduce the turn off time and thus switching loss. In addition, the proposed bipolar gate driver has no inductor in the driver circuit; therefore it can be fully integrated into a chip. For buck converter with 5V input, 1.3V/25A load, in 2 MHz frequency, the proposed gate driver increases the efficiency from 75.8% to 77.8% and from 72.9% to 76.5% at 5V input, 1.3V/25A load, in 2.5 MHz switching frequency.