Show simple item record

dc.contributor.authorGrant, Ryan Eric
dc.contributor.otherQueen's University (Kingston, Ont.). Theses (Queen's University (Kingston, Ont.))en
dc.date2007-08-16 16:06:15.414en
dc.date.accessioned2007-08-28T20:13:28Z
dc.date.available2007-08-28T20:13:28Z
dc.date.issued2007-08-28T20:13:28Z
dc.identifier.urihttp://hdl.handle.net/1974/647
dc.descriptionThesis (Master, Electrical & Computer Engineering) -- Queen's University, 2007-08-16 16:06:15.414en
dc.description.abstractEmerging processor technologies are becoming commercially available that make multi-processor capabilities affordable for use in a large number of computer systems. Increasing power consumption by this next generation of processors is a growing concern as the cost of operating such systems continues to increase. It is important to understand the characteristics of these emerging technologies in order to enhance their performance. By understanding the characteristics of high performance computing workloads on real systems, the overall efficiency with which such workloads are executed can be increased. In addition, it is important to determine the best trade-off between system performance and power consumption using the variety of system configurations that are possible with these new technologies. This thesis seeks to provide a comprehensive presentation of the performance characteristics of several real commercially available simultaneous-multithreading multi-processor architectures and provide recommendations to improve overall system performance. As well, it will provide solutions to reduce the power consumption of such systems while minimizing the performance impact of these techniques on the system. The results of the research conducted show that the new scheduler proposed in this thesis is capable of providing significant increases in efficiency for traditional and emerging multi-processor technologies. These findings are confirmed using real system performance and power measurements.en
dc.format.extent871480 bytes
dc.format.mimetypeapplication/pdf
dc.languageenen
dc.language.isoenen
dc.relation.ispartofseriesCanadian thesesen
dc.rightsThis publication is made available by the authority of the copyright owner solely for the purpose of private study and research and may not be copied or reproduced except as permitted by the copyright laws without written authority from the copyright owner.en
dc.subjectComputer engineeringen
dc.subjectComputer architectureen
dc.titleAnalysis and improvement of performance and power consumption of chip multi-threading SMP architecturesen
dc.typeThesisen
dc.description.degreeMasteren
dc.contributor.supervisorAfsahi, Ahmaden
dc.contributor.departmentElectrical and Computer Engineeringen


Files in this item

Thumbnail

This item appears in the following Collection(s)

Show simple item record