Next-Generation Photonic Signal Processors

Thumbnail Image
Ibrah, Ahmed
Photonics , Neuromorphic , Neural networks , Wavelength-division multiplexing , Mode-division multiplexing , Inverse design , MIMO , Blind source separation , Optical unscrambling , Micro-electro-mechanical systems , Dynamic electro-optic analog memory , Photonic tensor cores , Hybrid electronic-photonic neural networks
Digital electronics have advanced through miniaturization and neuromorphic architectures, enabling faster and more energy-efficient computing. However, they encounter challenges such as Moore's law saturation, speed constraints, and energy efficiency limitations due to wiring capacitance and transistor leakage. Photonic processors, leveraging light, are devoid of these effects and utilize wavelength-division multiplexing for increased throughput and energy efficiency. Yet, their WDM scalability is limited by the free spectral range (FSR) of photonic weights. Additionally, their energy efficiency and speed are limited by thermal weights and electronic memory, necessitating regular electronic-optical transitions. Their reliance on a single weight type also restricts their reconfigurability and application scope. In this thesis, we extend photonic hardware scalability by integrating mode-division with wavelength-division multiplexing, thus overcoming FSR limits and increasing throughput. We developed multimode WDM-compatible processors and components, such as multimode adiabatic multiplexers with insertion loss down to 0.5 dB and crosstalk isolation up to 57 dB, multimode micro-ring resonator weights, and photodetectors with responsivity up to 1 A/W. We also realized inverse-designed mode multiplexers, reducing multiplexer size by 2100\%. Our processor's capabilities were demonstrated in high-speed applications, including Radio-frequency signal unjamming, optical signal unscrambling, and photonic tensor core processing. Furthermore, we introduced electrostatic MEMS weights to reduce power consumption, enhance tuning speed, and provide cryogenic compatibility. These MEMS weights were integrated into neural networks, achieving fast update rates of up to 0.5 Mega updates per second. Additionally, we compared their performance with thermal weights in terms of power consumption. We also demonstrated monolithically integrated capacitive analog memory cells within photonic weights to minimize electronic-optical transitions, achieving a memory retention time of 0.8435 ms and a power consumption of 32.1 nW. We also emulated its performance in neural networks under limitations of memory leakage, noise, and control bit precision. Lastly, we proposed a reconfigurable tensor core (PTC) architecture that supports multiple weight types. We demonstrated a 3×3 PTC and used it in neural network emulations, employing a general matrix multiply compiler to adapt matrix-vector multiplication operations to the PTC size. We also explored the advantages of hybrid electronic-photonic neural networks over purely electronic or photonic networks.
External DOI