Low Power Communication RFIC Design For Applications In Biotelemetry

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Whitehall, Sean
Biotelemetry , Low power , RFIC , Low Noise , CMOS , FM-UWB
This thesis explores low power communication blocks for applications in biotelemetry. As wireless networks become more prevalent and demand for sensor networks increases, so does the need for low power wireless communication. First, a microwave wake-up receiver (WuRx) for biotelemetry applications is presented using 130 nm CMOS technology. The receiver is designed to operate at 7.6 GHz and measured results show that it has a sensitivity of -40 dBm while drawing just 3 uA from a 0.5 V supply. The presented work has the smallest known area and exhibits a competitive trade off between DC power, sensitivity, and bit rate. Second, a Frequency Modulated Ultra-Wideband (FM-UWB) receiver optimized for low power and fast start-up is also presented in 130nm CMOS. The receiver consists of a front end amplifier converting a frequency modulated (FM) signal to an amplitude modulated (AM) signal which is applied to an envelope detector. The receiver front end is for 500 MHz channels in the 3-4.5 GHz range. The Amplifier uses passive gain and four cascaded gain stages to achieve high RF gain without the need for super-regeneration and simplify the architecture this way, the front end has a 5 us wake-up time to enable efficient duty-cycling. The measured front end receives a signal at -68 dBm while consuming 600 uW of power (excluding a test buffer) from a 1 V supply. Last, a Frequency Modulated Ultra-Wideband (FM-UWB) transmitter optimised for low power consumption is presented. The chip includes a sub oscillator tunable from 0.1 to 4 MHz, a radio frequency oscillator tunable from 3.0 to 4.5 GHz, and an output power amplifier with matching network. Depending on channel selected, the measured transmitter consumes between 440 uW and 640 uW of power to produce - 14 dBm continuously to a 50 Ohm load, which is the lowest reported power. Two power supplies are used to reduce the effect of wasted voltage headroom between circuit blocks. Fabrication was done using the IBM 130 nm CMOS technology on a 1mm x 1mm loose die, the the circuit occupies 0.2 mm2 which is a tie for the smallest area.
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