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dc.contributor.authorChen, Fei
dc.contributor.otherQueen's University (Kingston, Ont.). Theses (Queen's University (Kingston, Ont.))en
dc.date2010-06-29 10:59:45.312en
dc.date.accessioned2010-06-30T15:05:57Z
dc.date.available2010-06-30T15:05:57Z
dc.date.issued2010-06-30T15:05:57Z
dc.identifier.urihttp://hdl.handle.net/1974/5910
dc.descriptionThesis (Master, Electrical & Computer Engineering) -- Queen's University, 2010-06-29 10:59:45.312en
dc.description.abstractThis thesis examines the design of a QPSK demodulator frontend for GPON transceiver at end user's side. Since lowering the cost of the terminal transceivers in an access network like GPON is a key requirement, CMOS technology is used and several area-saving design techniques are applied. The designed frontend circuit saved more than 80% area of the key components like the mixers and the QVCO than some published designs which can also fit the application. A measurement in frequency domain and a simulation in time domain verified that this frontend is able to demodulate a QPSK signal with a data rate as high as 5 Gbit/s. Two structures of quadrature oscillators are firstly presented and compared. One is an LC QVCO centered at 5 GHz, which has a tuning range of 3 GHz, a phase noise of -100.8 dBc/Hz at 1 MHz offset, and an area of 0.15 mm2 excluding pads. The other is a ring QVCO which only takes an area of 0.019 mm2. But it has a higher phase noise of -81 dBc/Hz at 1 MHz offset. Then two broadband mixers are described separately. The first one provides a high conversion gain, but its input linearity is insufficient to meet the input power requirement. The second mixer obtains required input linearity but with a trade-off of conversion gain. Both mixers have a broadband input impedance match from 2 GHz to 8 GHz. The first mixer has a conversion gain of 8.5 dB and an input 1 dB compresion point at -17 dBm. The second mixer has a conversion gain of -7 dB with an on-chip buffer or -2.1 dB without buffer, but an input 1 dB compresion point at -5 dBm. A frontend circuit is lastly presented. It integrates the compact ring QVCO, two broadband mixers with high input linearity, and two second-order LC ladder low pass filters. A Frequency domain measurement shows the expected spectrum down conversion of a 2.5 Gsym/s QPSK signal centered at 5 GHz. The whole frontend circuit including pads takes 1 mm2 area, and consumed 157 mW power.en
dc.languageenen
dc.language.isoenen
dc.relation.ispartofseriesCanadian thesesen
dc.rightsThis publication is made available by the authority of the copyright owner solely for the purpose of private study and research and may not be copied or reproduced except as permitted by the copyright laws without written authority from the copyright owner.en
dc.subjectfrontenden
dc.subjectQPSK demodulationen
dc.subjectGPONen
dc.subjectCMOSen
dc.subjectVCOen
dc.subjectmixeren
dc.titleA CMOS QPSK Demodulator Frontend for GPONen
dc.typethesisen
dc.description.degreeMasteren
dc.contributor.supervisorFrank, Brian M.en
dc.contributor.departmentElectrical and Computer Engineeringen


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